The present invention relates to an IC tester for supplying a plurality of test pattern signals respectively through different drivers to corresponding terminal pins of an IC being tested and receiving response outputs from the IC to thereby test the IC.
IC testers such as disclosed in U.S. Pat. No. 4,092,589 entitled "High-speed Testing Circuit" issued May 30, 1978 generate a plurality of test pattern signals, supply them to corresponding terminal pins of an IC being tested at suitable timing, convert outputs from the IC to logic levels with a comparator, and compare converted outputs with expected values for thereby determining whether the IC being tested is acceptable or not. Proper test results cannot often be obtained when the test pattern signals are not supplied to the IC terminal pins at predetermined timing. It is therefore desirable that the test pattern signals be propagated from the signal generator to the terminal pins in equal periods of time. To this end, test pattern signal paths are tested prior to an IC test by electrically severing an IC to be tested from test pattern output terminals of the IC tester, supplying a reference timing signal to each of the test pattern signal paths, and adjust the propagation time of each test pattern signal path in order that the reference timing signals appearing at the test pattern output terminals will be in phase with each other.
In actual IC tests, the test pattern output terminals of the IC tester are connected to the corresponding terminals in an IC socket through connector lines such as a printed circuit or a coaxial cable, and the terminal pins of an IC to be tested are inserted into the IC socket. However, the grounding capacitance (stray capacitance) of each connector line and that of each IC socket terminal do not agree with each other, resulting in different propagation times required for the test pattern signals to travel from the test pattern output terminals to the IC terminal pins. Such variations in the propagation time have a larger effect as the test pattern signals approach completely rectangular waveforms with rise and fall times being zero, thus varying the relative timing at which the test pattern signals arrive at the terminal pins of the IC being tested. It would be possible to adjust the drivers for delivering the test pattern signals to round off the waveform of the test pattern signals, that is, to incline leading and trailing edges of the test pattern signals until the variations in signal arrival timing become reduced. However, adjustment of the drivers including active elements to obtain predetermined waveforms would be relatively difficult to perform, and no predetermined waveforms could stably be produced. Furthermore, such an effort would be disadvantageous in that the rise and fall times would be varied by a variation in the amplitude of the output waveforms from the drivers.